1. Field of the Invention
The present invention relates to a signal change detection circuit for detecting the change of one signal of a rising or a falling of an input signal, and generating a pulse signal having a predetermined pulse width.
2. Description of the Related Art
In an integrated circuit operating in synchronization with a synchronization signal input from an external portion, for example, a clock signal, a pulse having a constant width is sometimes generated in an internal portion in synchronization with the external clock signal. In general, such a function can be realized by a monostable multi-vibrator. The monostable multi-vibrator generates a pulse having an intended width not depending upon the waveform of the external clock signal, but in synchronization with a level change edge of the external clock signal, for example, a rising edge or a trailing edge. The stability of the operation of the internal circuit can be improved by generating the pulse inside the LSI in synchronization with the external clock signal in this way and controlling the internal operation of the LSI in accordance with this.
Some of factors behind fluctuation of the external clock signal waveform are the usage conditions, properties of the apparatus, noise, etc. For example, a frequency of the external clock signal, duty ratio, high level voltage, and low level voltage change in accordance with the usage conditions of the LSI. Alternatively, the rising time and falling time of the external clock signal are influenced by the properties of the apparatus. Further, the waveform of the external clock signal is sometimes corrupted by noise such as ringing, overshoot, and undershoot.
The fluctuation of the waveform of the external clock signal exerts an adverse influence upon the operation of the internal circuit of the LSI, and therefore is usually not preferred. For this reason, after performing processing so as to generate a pulse having a constant width in the internal portion in synchronization with the external clock signal, it is supplied to the internal circuit. Such a circuit is generally referred to as a signal change detection circuit. The monostable multi-vibrator is one example of a signal change detection circuit.
Further, conventionally, a pulse having a predetermined width was generated in synchronization with the input signal by using the signal change detection circuit shown in FIG. 14 and FIG. 16 and supplied to the internal circuit.
The circuit of FIG. 14 is constituted by an inverter INV1, a delay circuit DLY1, and an AND gate AND1. The input signal A is input to one input terminal of the AND gate AND1, inverted by the inverter INV1, further delayed by a predetermined delay time td by the delay circuit DLY1, and then input to the other input terminal of the AND gate AND1. For this reason, as shown in FIG. 15A, where the input signal A has a constant width, a pulse C having a width set by the delay time td of the delay circuit DLY1 is generated.
On the other hand, where the width of an input signal A' is shorter than the delay time td of the delay circuit DLY1, as shown in FIG. 15B, a pulse C' having a narrower width than td is generated and a normal output is not obtained. In order to solve this problem, it can be considered to once extend the width of the high level of the external clock signal. FIG. 16 shows an example of the signal change detection circuit provided with such a function.
The signal change detection circuit shown in FIG. 16 is constituted by a delay circuit DLY2, an OR gate OR1, an inverter INV2, a delay circuit DLY3, and an AND gate AND2.
When defining the width of the input signal A as tCH and the delay time of the delay circuit DLY2 as td1, as shown in FIG. 17, a pulse C having a width (tCH+td1) is generated by the delay circuit DLY2 and the OR gate OR1.
A pulse E having a constant width is generated by the signal change detection circuit comprising the inverter INV2, the delay circuit DLY3, and the AND gate AND2 with respect to a pulse C having the extended width. Here, for example, when defining the delay time of the delay circuit DLY3 as td2, as shown in FIG. 17, a pulse E having a width td2 is generated. Then, even in a case where the width of the input signal A is narrow, by setting the delay time td1 of the delay circuit DLY2 sufficiently long, a pulse E having a normal width can be generated. Namely, the problem possessed by the signal change detection circuit shown in FIG. 14 can be avoided to a certain extent.
Here, when defining the period of the input signal A as tCP, the condition of normal operation of the signal change detection circuit of FIG. 16 is given by the next equation. EQU td2-td1&lt;tCH&lt;tCP-td1 (1)
In the conventional signal change detection circuit, there is a disadvantage that the number of stages of the circuit becomes large in order to realize a certain operation and the delay time of the output signal becomes large with respect to the input signal. For example, for the purpose of outputting data from the rising edge of the clock signal at a high speed, for example, the clock access time of a synchronous type SRAM, it is important to transmit the internal clock signal with a small number of stages and it is important to reduce the signal delay due to the provision of the signal change detection circuit as much as possible.